Title :
Implementation of a high-speed FIR filter using a BiCMOS-ECL mixed gate array with embedded SRAM
Author_Institution :
ASIC Div., National Semiconductor, Santa Clara, CA
Abstract :
Describes several options of implementing a finite impulse response (FIR) digital filter. A design example of a FIR filter using a single high-speed multiplier/accumulator and embedded BiCMOS SRAMs in a BiCMOS-ECL gate array is presented
Keywords :
BiCMOS integrated circuits; SRAM chips; VLSI; application specific integrated circuits; digital filters; logic arrays; ASIC; BiCMOS SRAMs; BiCMOS-ECL gate array; FIR filter; design example; embedded SRAM; high speed filters; implementation; mixed gate array; multiplier/accumulator; options; Application specific integrated circuits; BiCMOS integrated circuits; Digital filters; Feedback; Filtering; Finite impulse response filter; Kernel; Random access memory; Shift registers; Signal sampling;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242947
