VLSI echo cancellation filter

Received television images are often degraded by echoed images due to multiple path reception. To solve this problem a combination of echo cancellation filter hardware and channel identification software is necessary. In this paper the authors discuss details of a digital filter ASIC designed for this application. The filter chip was designed using datapath, memory and state machine compiler technology. The chip is fabricated in a 1 micron CMOS process from VLSI Technology Inc. The filter chip has four clusters of programmable transversal filters and delay sections that can be configured for various modes of operation specific to echo cancellation. The chip consist of 56 eight by eight signed multipliers, 2 K bytes of memory, and a total of over 360 K transistors. The chip has successfully been incorporated into a prototype NTSC echo cancellation receiver