DocumentCode :
3351143
Title :
A 25 MHz 5×7 spatial filter chip for realtime image processing
Author :
Kawata, Tetsuro ; Son, Jinshu ; Tomari, Naosada ; Yamauchi, Kazumi ; Miyakawa, Nobuaki ; Sasuga, Kazuyasu ; Taniuchi, Kazuman
Author_Institution :
Fuji Xerox Co. Ltd., Kanagawa, Japan
fYear :
1991
fDate :
23-27 Sep 1991
Lastpage :
37987
Abstract :
A 25 MHz 5×7 spatial filter chip has been developed using CMOS 2 μm process for realtime image processing. The filtering coefficients are specified in a 12-bit floating-point format for higher precision arithmetic. Each multiplier has three coefficient registers for changing the coefficient values in realtime. It contains about 71000 transistors on a 11.7×13.3 mm2 die
Keywords :
CMOS integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; image processing equipment; real-time systems; two-dimensional digital filters; 11.7 mm; 12 bit; 13.3 mm; 2 micron; 25 MHz; 2D digital filters; 35 pixel; 5 pixel; 7 pixel; ASIC; CMOS; coefficient registers; floating-point format; multiplier; precision arithmetic; realtime image processing; spatial filter chip; Arithmetic; Costs; Degradation; Digital filters; Digital images; Filtering; Image processing; Large scale integration; Registers; Spatial filters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
Type :
conf
DOI :
10.1109/ASIC.1991.242952
Filename :
242952
Link To Document :
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