DocumentCode
3351188
Title
Fast partitioning method for PLA-based architectures
Author
Hasan, Zafar ; Harrison, Dave ; Ciesielski, Maciej J.
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38047
Abstract
Describes a method for automatic partitioning of a given multioutput function into the smallest number of subfunctions such that each subfunction can fit into a fixed size PLA or functional block of a given field programmable gate array (FPGA) chip. The proposed method is fast, efficient and produces almost optimum partitions for the examples which have been tried. The partitioning procedure is in production use as part of an automated design system at Plus Logic
Keywords
logic CAD; logic arrays; PLA-based architectures; Plus Logic; automated design system; automatic partitioning; multioutput function; optimum partitions; partitioning procedure; subfunctions; Application specific integrated circuits; Computer architecture; Costs; Field programmable gate arrays; Logic circuits; Logic design; Logic devices; Partitioning algorithms; Programmable logic arrays; Software tools;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242956
Filename
242956
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