DocumentCode
3351209
Title
Architectural innovations for high performance in PLDs
Author
Lewis, Julie A.
Author_Institution
Cypress Semiconductor Corp., San Jose, CA, USA
fYear
1991
fDate
23-27 Sep 1991
Lastpage
38018
Abstract
Because of the recent explosion of PLD architectures, it is more difficult than ever for users to choose the architecture that will best suit their needs. To aid in that choice, this paper discusses performance trade-offs with respect to features of a PLD, and also examines what to look for when reading data sheets for programmable devices
Keywords
logic arrays; logic design; PLD architectures; data sheets; performance trade-offs; programmable devices; Clocks; Decoding; Explosions; Field programmable gate arrays; Fuses; Heart; Logic arrays; Logic devices; Strontium; Technological innovation;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location
Rochester, NY
Print_ISBN
0-7803-0101-3
Type
conf
DOI
10.1109/ASIC.1991.242958
Filename
242958
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