Title :
ASIC clock distribution using a phase locked loop (PLL)
Author_Institution :
Motorola Inc., Chandler, AZ, USA
Abstract :
Transferring data between ASIC chips at frequencies above 40 MHz requires special on-chip circuitry in current sub-micron technologies. Phase locked loops can provide clock skew management in ASIC devices to help compensate for clock tree insertion delays and process, temperature and voltage variations allowing maximum multi-chip system performance
Keywords :
application specific integrated circuits; clocks; delays; phase-locked loops; ASIC clock distribution; clock skew management; clock tree insertion delays; multi-chip system performance; on-chip circuitry; phase locked loop; process variations; sub-micron technologies; temperature variations; voltage variations; Application specific integrated circuits; Clocks; Delay effects; Frequency conversion; Integrated circuit technology; Phase locked loops; Registers; Temperature; Timing; Voltage;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242961
