Title :
A time-to-digital converter using vernier delay line with time amplification technique
Author :
Chung, M.H. ; Chou, H.P.
Author_Institution :
Dept. of Eng. & Syst. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
The paper presents a vernier delay line (VDL) type of time to digital converter (TDC) using time amplification technique. The proposed time amplifier (TA) architecture is aim to provide larger input range and higher gain. Simulation results indicated that the maximum deviation between ideal and actual TA transfer curve has been reduced to about 30ps, and the input range and gain are 160ps and 16 respectively. The TDC has maximum sampling rate of about 50Msps when using 200MHz reference clock and the time resolution of 39ps with the differential non-linearity (DNL) within -0.6 and 1 LSB, and the integral non-linearity (INL) within -1.4 and 1 LSB. The TDC is realized using the CMOS 0.18um 1P6M technology.
Keywords :
circuit simulation; delay lines; time-digital conversion; CMOS 0.18um 1P6M technology; amplification technique; size 0.18 mum; time amplification technique; time amplifier architecture; time-to-digital converter; vernier delay line; Clocks;
Conference_Titel :
Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE
Conference_Location :
Valencia
Print_ISBN :
978-1-4673-0118-3
DOI :
10.1109/NSSMIC.2011.6154295
