Title :
Power dissipation of CMOS ASICs
Author_Institution :
VLSI Technology Inc., Wilmington, MA, USA
Abstract :
High levels of power dissipation in CMOS ASICs are a result of high speed and complexity which exacerbates numerous design issues due to elevated junction temperatures. A method of calculating total power dissipation, as viewed from the gate level in an ASIC design methodology is presented and the effects of power dissipation are examined. Techniques for reducing power dissipation are described and other design and analysis issues are considered
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated logic circuits; logic gates; ASIC design methodology; CMOS ASICs; complexity; elevated junction temperatures; gate level; power dissipation; speed; total power dissipation; Application specific integrated circuits; CMOS technology; Costs; Degradation; Electromigration; MOS devices; Packaging; Power dissipation; Temperature; Very large scale integration;
Conference_Titel :
ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-0101-3
DOI :
10.1109/ASIC.1991.242969
