• DocumentCode
    3351348
  • Title

    VERITAS: A 128-channel ASIC for the readout of pnCCDs and DEPFET arrays for X-ray imaging, spectroscopy and X-ray FEL applications. Experimental results and new designs

  • Author

    Porro, Matteo ; Bianchi, Davide ; De Vita, Giulio ; Herrmann, Sven ; Wassatsch, Andreas ; Hartmann, Robert ; Hauser, Gunter ; Strüder, Lothar

  • Author_Institution
    Max-Planck Inst. fuer Extraterrestrische Phys., Garching, Germany
  • fYear
    2011
  • fDate
    23-29 Oct. 2011
  • Firstpage
    951
  • Lastpage
    958
  • Abstract
    VERITAS is the first 128-channel ASIC developed to readout both the pnCCDs and the DEPFET arrays produced at the MPI-Halbleiterlabor in Munich. These detectors are used in a large variety of scientific applications, ranging from X-ray astronomy to the new X-ray Free Electron Laser sources. The main concept of VERITAS is to provide a flexible readout chip able to cope not only with different kinds of detectors, but also with a large set of operating conditions that may require very different noise thresholds and input dynamic ranges. These can vary by more than two orders of magnitude. Every analog channel of VERITAS provides trapezoidal weighting function. This filtering strategy had never been applied to the pnCCD before. The very first measurements obtained coupling VERITAS with a 128×256 pnCCD are shown. With these settings an input charge up to 2.5×105 electrons can be processed. With a readout time of 4 µs/line a noise of 3.9 electrons has been measured in the highest gain mode. The resolution obtained on the Mn-Kα peak of a 55Fe source is of 136 eV for single events. A noise of 30 electrons has been achieved in the lowest gain mode at a speed of 6.4 µs/line. In this low gain setting an input charge up to 2.5×105 electrons can be processed. These striking results fulfill the requirements of the main foreseen applications of large-size pnCCDs: experiments with Free Electron Lasers and high-speed optical astronomy. In order to further improve the performance and the flexibility of the ASIC, a second version based on a fully differential architecture has been designed. This topology allows a simpler filter implementation and it is less sensitive to cross-talk. In addition it offers the possibility to switch with the same ASIC between the source follower and drain current readout of the DEPFET sensors. The drain readout should make it possible to reach a processing time of about 2&#x- 013;3 µs/line with an electronics noise ≤10 el. This makes the second version of VERITAS very attractive for the proposed ESA X-ray astronomy mission ATHENA.
  • Keywords
    CCD image sensors; X-ray apparatus; application specific integrated circuits; field effect transistors; readout electronics; 55Fe Mn-K-alpha peak; ASIC; DEPFET array readout; DEPFET sensors; ESA ATHENA mission; MPI-Halbleiterlabor; VERITAS analog channel; X-ray FEL; X-ray astronomy mission; X-ray imaging; X-ray spectroscopy; drain current readout; flexible readout chip; fully differential architecture; high speed optical astronomy; large size pnCCD; pnCCD readout; source follower; trapezoidal weighting function; Anodes; CMOS integrated circuits; CMOS technology; Capacitance; Extraterrestrial measurements; Preamplifiers; Size measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2011 IEEE
  • Conference_Location
    Valencia
  • ISSN
    1082-3654
  • Print_ISBN
    978-1-4673-0118-3
  • Type

    conf

  • DOI
    10.1109/NSSMIC.2011.6154301
  • Filename
    6154301