The state-of-art and future trends in testing embedded memories

Author

Hamdioui, Said ; Gaydadjiev, Georgi ; Van de Goor, Ad J.

Author_Institution

Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands

fYear

2004

fDate

9-10 Aug. 2004

Firstpage

54

Lastpage

59

Abstract

According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatical impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modelling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. This paper presents the state of art in memory testing including fault modeling, test design, built-in-self-test (BIST) and built-in-self-repair (BISR). Further research challenges and opportunities are discussed in enabling testing (embedded) memories, which use deep submicron technologies.

Keywords

built-in self test; embedded systems; fault simulation; integrated circuit design; integrated circuit testing; integrated circuit yield; integrated memory circuits; system-on-chip; SoC yield; built-in-self-repair; built-in-self-test; deep submicron technology; defect-per-million level; embedded memory testing; fault modeling; memory designs; memory yield; system on chips; test design; Algorithm design and analysis; Art; Built-in self-test; Computer science; Costs; Embedded computing; Fault diagnosis; Logic testing; Mathematics; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on

ISSN

1087-4852

Print_ISBN

0-7695-2193-2

Type

conf

DOI

10.1109/MTDT.2004.1327984

Filename

1327984