• DocumentCode
    3352025
  • Title

    A programmable built-in self-diagnosis for embedded SRAM

  • Author

    Selva, Carolina ; Torelli, Cosimo ; Rimondi, Danilo ; Zappa, Rita ; Corbani, Stefano ; Mastrodomenico, Giovanni ; Albani, Lara

  • Author_Institution
    STMicroelectronics, Agrate Brianza, Italy
  • fYear
    2004
  • fDate
    9-10 Aug. 2004
  • Firstpage
    84
  • Lastpage
    89
  • Abstract
    In this work we present a built-in self-diagnosis (BISD) module, an integrated solution for the fault diagnosis of embedded memories. The BISD methodology proposed includes a built-in self-test block and an additional circuitry to perform the on-chip failure analysis in order to detect the main defects. The fault diagnosis system developed is aimed to the maturation of the technology as well as to the diagnosis of circuits in case of sudden yield drop. The fault diagnosis is a key factor for the technology maturation. New technologies require a certain time to get stability before being used for massive production. On the other hand, problems of sudden yield drop can occur also when the technology is stable. In this case a fast recovery on yield is required. This BISD module is highly re-configurable, its main characteristics are the programmability with different test algorithms, the flexibility with respect to memory sizes and address scrambling and the reconfigurability with respect to the part of the array to diagnose. The BISD block has been implemented in a 0.13 μm flash technology with a 512Kbit SRAM, it has an area overhead of 13% and its maximum operation frequency is 150MHz.
  • Keywords
    SRAM chips; built-in self test; design for testability; embedded systems; fault diagnosis; flash memories; integrated circuit testing; 0.13 micron; 150 MHz; 512 Kbit; BISD methodology; built-in self-test block; embedded SRAM; embedded memories; fault diagnosis system; flash technology; memory sizes; on-chip failure analysis; programmable built-in self-diagnosis; test algorithms; yield drop; Automatic testing; Built-in self-test; Circuit testing; Costs; Design for testability; Failure analysis; Fault diagnosis; Integrated circuit technology; Production; Random access memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Technology, Design and Testing, 2004. Records of the 2004 International Workshop on
  • ISSN
    1087-4852
  • Print_ISBN
    0-7695-2193-2
  • Type

    conf

  • DOI
    10.1109/MTDT.2004.1327989
  • Filename
    1327989