Embedded real time digital signal processing unit for a 64-channel PET detector module

Recent developments in avalanche photodiode (APD) technology have led to the design and fabrication of a new radiation detector module based on an 8 × 8 array of LYSO crystals individually coupled to the pixels of two 4 × 8 monolithic APD arrays. This evolution entails the complete redesign of the data acquisition system to satisfy the 7-fold increase in pixel density relative to a previous implementation of individually read out sensors. As a result, the required digital signal processing cannot be implemented exclusively in FPGAs due to cost, area occupied and power consumption considerations. To comply with this new reality, a 64-channel mixed-signal ASIC, built from TSMC CMOS 0.18 μm technology, has been designed. It uses a Time-over-Threshold (ToT) scheme to extract both energy and timing along with the pixel number. A complex architecture of finite state-machines, driven by a 100 MHz clock, ensures the ASIC real time ToT calculation operations and its proper calibration by an external device. The ASIC can output as much as 2 Mevents/s on its LVDS data transfer dedicated link and consumes around 600 mW. The ASIC was developed following a mixed-signal flow allowing the designers to minimize and to verify the impact of undesirable parasitic effects on both analog and digital ends of the ASIC before sending the layout to the foundry.