Title :
Process simplification in deep submicron CMOS fabrication
Author :
Koike, H. ; Ohtsuka, H. ; Matsuoka, F. ; Kakumu, M. ; Maeguchi, K.
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
Process simplification in deep submicron CMOS fabrication is discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation process are extracted as items to simplify the process. A combination of shallow trench isolation and single mask step well/gate doping is proposed for deep submicron CMOS fabrication. This new process can achieve a reduction of 5 mask steps and eliminates both well drive-in annealing and field oxidation without performance deterioration. As a result, 10% process step reduction and 20% manufacturing turn-around-time reduction have been realized in comparison to the standard 1Poly/1Metal CMOS process with LOCOS isolation
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; isolation technology; masks; semiconductor doping; CMOS fabrication; LOCOS isolation; deep submicron CMOS; gate formation process; isolation process; manufacturing turn-around-time reduction; process step analysis; shallow trench isolation; single mask step well/gate doping; Annealing; CMOS process; Costs; Diffusion processes; Doping; Fabrication; Ion implantation; Manufacturing processes; Oxidation; Semiconductor device manufacture;
Conference_Titel :
Semiconductor Manufacturing, 1995., IEEE/UCS/SEMI International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2928-7
DOI :
10.1109/ISSM.1995.524351
