Title :
Yield enhancement vs. performance improvement in VLSI circuits
Author :
Chiluvuri, Venkat K R ; Koren, Israel
Author_Institution :
Semicond. Syst. Des. Technol., Motorola Inc., Austin, TX, USA
Abstract :
For advanced submicron VLSI technologies maintaining higher performance and better yield is a challenging task. Layout optimization for improving yield may affect the circuit performance and vice versa. We analyse the effect of layout modifications for parasitic capacitance reduction on yield in this paper. Our results show that the solutions to the yield enhancement and parasitic capacitance reduction problems are very close to each other
Keywords :
VLSI; capacitance; circuit optimisation; integrated circuit layout; integrated circuit technology; integrated circuit yield; VLSI circuits; capacitance reduction problems; circuit performance; layout optimization; parasitic capacitance reduction; performance improvement; submicron VLSI technologies; yield enhancement; Compaction; Delay; Integrated circuit interconnections; Integrated circuit yield; Manufacturing; Minimization; Parasitic capacitance; Routing; Very large scale integration; Wire;
Conference_Titel :
Semiconductor Manufacturing, 1995., IEEE/UCS/SEMI International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2928-7
DOI :
10.1109/ISSM.1995.524352
