DocumentCode :
3352536
Title :
Design and Analysis of Interconnection Network of Reconfigurable Cryptographic Processor
Author :
Yingjie, Qu
Author_Institution :
Sch. of Inf. Sci. & Technol., Qingdao Univ. of Sci. & Technol., Qingdao, China
Volume :
2
fYear :
2009
fDate :
28-30 Oct. 2009
Firstpage :
394
Lastpage :
398
Abstract :
The reconfigurable cryptographic processor is an integrated circuit that is used for data encryption or decryption. The logic structure and function of this processor is reconfigurable, so it can implement many different cipher algorithms flexibly and quickly. The interconnection network of the reconfigurable cryptographic processor is the data transmission path, so it has very important influence on the flexibility, performance and scale of the processor. In this paper, several conceptions such as connectivity, network width, network scale have been proposed, some design principles of the interconnection network have been given, three typical interconnection networks named all interconnected, single bus, multiple bus have been introduced and their features have been analyzed.
Keywords :
cryptography; integrated circuits; multiprocessor interconnection networks; cipher algorithms; data decryption; data encryption; data transmission path; integrated circuit; interconnection network analysis; interconnection network design; processor logic structure; reconfigurable cryptographic processor; Computer science; Cryptography; Data communication; Data engineering; Design engineering; Information analysis; Integrated circuit technology; Multiplexing; Multiprocessor interconnection networks; Reconfigurable logic; cryptographic; decryption; encryption; interconnection network; processor; reconfigurable;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Science and Engineering, 2009. WCSE '09. Second International Workshop on
Conference_Location :
Qingdao
Print_ISBN :
978-0-7695-3881-5
Type :
conf
DOI :
10.1109/WCSE.2009.838
Filename :
5403317
Link To Document :
بازگشت