Title :
Efficient Designs for Adder Comparator
Author :
Adachi, Hisako ; Nakamura, Shinji
Author_Institution :
Tamagawa Univ., Tokyo
Abstract :
When two fixed-point binary values are compared, in average, only two bit positions are dominant to decide its result. To exploit this property in efficient arithmetic operations two types of addition and comparison circuits are considered. A parallel input design that utilizes dynamic asynchronous mechanisms has been implemented by MOSIS AMI 1.5mum process. The other design assumes serial inputs and has internal clocking with asynchronous input/output interface.
Keywords :
adders; asynchronous circuits; comparators (circuits); digital arithmetic; fixed point arithmetic; MOSIS AMI process; adder comparator; asynchronous input-output interface; dynamic asynchronous mechanisms; efficient arithmetic operations; fixed-point binary values; internal clocking; parallel input design; sequential adder; Added delay; Adders; Ambient intelligence; Arithmetic; Circuits; Clocks; Design optimization; Logic design; Logic functions; Process design; Adder; comparator; dynamic logic; precharge; sequential addition;
Conference_Titel :
Information Sciences and Systems, 2007. CISS '07. 41st Annual Conference on
Conference_Location :
Baltimore, MD
Print_ISBN :
1-4244-1063-3
Electronic_ISBN :
1-4244-1037-1
DOI :
10.1109/CISS.2007.4298408
