Title :
A hierarchical scheduling system using new weight assigned function in VLSI development lines
Author :
Ishizuka, Hiroaki ; Matsumoto, Shigeru ; Nakata, Kazuki ; Tanimura, Shoichi ; Hirofuji, Yuichi
Author_Institution :
Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
Abstract :
Many kinds of scheduling systems have been devised in order to realize an efficient operation of production lines by means of, for example, shortening turn around time (TAT). The VLSI development line requires the following special key items: (1) an efficient lot processing schedule as the number of process steps in given period are maximized; (2) the quick making of a schedule counteracting the alternation of recipes and changes of the period demanded for the experimentation. We developed a new hierarchical scheduling system (DYSCHE II: DYnamic SCHEduling system II) using a Weight Assigned Function (WAF) to overcome the problem of conventional scheduling systems
Keywords :
VLSI; integrated circuit manufacture; production control; DYSCHE II; VLSI development line; dynamic scheduling; hierarchical scheduling system; lot processing; production line; turn around time; weight assigned function; Dynamic scheduling; Iterative algorithms; Laboratories; Physics; Production systems; Scheduling algorithm; Springs; Very large scale integration;
Conference_Titel :
Semiconductor Manufacturing, 1995., IEEE/UCS/SEMI International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2928-7
DOI :
10.1109/ISSM.1995.524365