DocumentCode :
3352670
Title :
Cost of “ad hoc” wafer release policies
Author :
Nag, Pranab K. ; Maly, Wojeiech
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
fYear :
1995
fDate :
17-19 Sep 1995
Firstpage :
97
Lastpage :
102
Abstract :
Modern manufacturing operations must, on one hand, be very flexible in order to react to the rapidly changing market needs, and on the other hand, as cost effective as possible. The chaotic nature of the market, however, does not allow systematic minimization of manufacturing costs. This paper studies manufacturing flexibility, manufacturing cost trade-off. The analysis is performed using a simulation technique and assuming that the chaotic nature of the market can be modeled by `ad hoc´ wafer release policies
Keywords :
costing; economics; integrated circuit manufacture; semiconductor process modelling; ad hoc wafer release policies; chaotic market; manufacturing costs; manufacturing flexibility; semiconductor fab; simulation; Automatic control; Chaos; Costs; Fabrication; Production facilities; Pulp manufacturing; Semiconductor device manufacture; Semiconductor device modeling; Surges; Virtual manufacturing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Semiconductor Manufacturing, 1995., IEEE/UCS/SEMI International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2928-7
Type :
conf
DOI :
10.1109/ISSM.1995.524368
Filename :
524368
Link To Document :
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