Title :
Rapid failure analysis using contamination-defect-fault (CDF) simulation
Author :
Khare, Jitendra ; Maly, Wojciech
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
This paper describes a new methodology for rapid failure analysis. The methodology is based on the simulator CODEF, which is able to map the effects of contamination deposited on an IC during any stage of the manufacturing process, onto circuit-level faults. The utilization of such a capability in failure analysis is illustrated with examples
Keywords :
failure analysis; fault diagnosis; semiconductor process modelling; surface contamination; CODEF simulator; IC manufacturing; circuit-level faults; contamination-defect-fault simulation; failure analysis; Analytical models; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Contamination; Fabrication; Failure analysis; Integrated circuit modeling; Resists;
Conference_Titel :
Semiconductor Manufacturing, 1995., IEEE/UCS/SEMI International Symposium on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-2928-7
DOI :
10.1109/ISSM.1995.524376
