DocumentCode
3352798
Title
A highly stable SRAM memory cell with top-gated P-N drain poly-Si TFTs for 1.5 V operation
Author
Hayashi, F. ; Ohkubo, H. ; Takahashi, T. ; Horiba, S. ; Noda, K. ; Uchida, T. ; Shimizu, T. ; Sugawara, N. ; Kumashiro, S.
Author_Institution
ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan
fYear
1996
fDate
8-11 Dec. 1996
Firstpage
283
Lastpage
286
Abstract
A novel memory cell has been proposed for low voltage operated, high speed and high density SRAMs. Features of this cell are (1) high performance poly-Si TFT loads utilizing bipolar action positively, and (2) a node contact structure which keeps current drivability of TFTs to the cell nodes high by the elimination of parasitic high resistance regions. The minimum operation voltage of 1.5 V has been confirmed by 0.3 /spl mu/m design rule 64 kbit SRAMs without a boosted word-line scheme.
Keywords
SRAM chips; thin film transistors; 0.3 micron; 1.5 V; 64 kbit; Si; bipolar action; current drivability; low voltage high speed high density SRAM; memory cell; node contact; top-gated P-N drain poly-Si TFT; Charge carrier lifetime; Electrons; Laboratories; Low voltage; MOSFETs; National electric code; Random access memory; Thin film transistors; Threshold voltage; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-3393-4
Type
conf
DOI
10.1109/IEDM.1996.553585
Filename
553585
Link To Document