A new LSI manufacturing scheme in the large-diameter wafer era for super-quick TAT development and volume production

We describe a new LSI manufacturing scheme which features the compatibility of quick TAT development and volume production. It is composed of a main production line and extra paths of single-wafer processing. In the super-quick TAT runs, all of the batch process steps in the main line are replaced by single-wafer processing. The process compatibility enables us to smoothly transfer from development to volume production. We discuss implementation issues, and show experimental and simulation results to verify the effectiveness of this concept in the development of logic and memory products. This approach will reduce the cost for process development, and enhance the evolution of single-wafer processing equipment towards the large-diameter wafer era