Reliability analysis of copper interconnection in system-in-package structure

The system-in-package (SiP) is one of the popular designs to meet the trend of integrated circuit (IC) development. It is known for its small size, light weight, and multiple functionality. In this paper, a radio frequency front end module (RF-FEM) incorporated with the novel wafer-level chip scale package (WLCSP) technology is investigated. Generally the solder joints in WLCSP are the weakest portions due to the CTE mismatch between the PCB board and the package. For the SiP structure investigated, the filler polymer is treated as a good stress buffer layer to relax most CTE-mismatch-induced thermal stress. However, the interconnection laminated within the filler polymer is pulled by the expansion of the polymer with relatively higher thermal stresses. The reliability of copper interconnection between chips then becomes a serious issue for the SiP structure. Finite element analysis (FEA) was applied to evaluate the stress distribution of the SiP structure under the thermal loading from 25degC to 125degC. Both package-level and board- level structures are studied. The same fatigue phenomenon is observed in similar package structures [C. yuan et al., 2006; H.P. Wei et al., 2006; M.C. Yew et al., 2006]. Investigating further, two failure mechanisms are disclosed in the package-level structure and board-level structure, respectively. The first failure mechanism is due to the CTE mismatch among the copper interconnections, filler polymer, and chips. Meanwhile, the second failure mechanism is due to the expansion of the filler polymer which will pull the copper interconnection, thereby aggravating the stress concentration behavior, especially at the chip/polymer edge. To reduce the effect of CTE mismatch, several parametric studies are performed to enhance the reliability of copper interconnections. Finally, a compromised optimal distance is found to minimize the stress concentration of vias on chips would be decided.