Title :
A 12-bit 40MSPS 3.3-V 56-mW pipelined A/D convereter in 0.25-μm CMOS [convereter read converter]
Author :
Lotfi, Reza ; Taherzadeh-Sani, Mohammad ; Shoaei, Omid
Author_Institution :
Dept. of Electr. & Comput. Eng.,, Tehran Univ., Iran
Abstract :
In this paper, a very low-power high-speed high-resolution pipelined analog-to-digital converter (ADC) based on an optimization methodology previously proposed by the authors, is presented. By expressing the total static power consumption and the total input-referred noise of the converter as function of the capacitor values and the resolutions of the converter stages, a simple optimization algorithm is employed to calculate the optimum values of these parameters, which lead to minimum power consumption while a specified noise requirement is satisfied. Design considerations and simulation results of the 12-bit 3.3V 40MS/s pipelined ADC with only 56mW consumption in a 0.25μm CMOS process, are presented. The simulated values of the SNR and SFDR are 69dB and 75dB respectively.
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit optimisation; circuit simulation; low-power electronics; pipeline processing; 0.25 microns; 12 bit; 3.3 V; 56 mW; 69 dB; CMOS process; high-resolution pipelined ADC; high-speed pipelined ADC; input-referred noise; low-power pipelined ADC; noise requirement; optimization methodology; parameter optimum values; power consumption minimizations; Adders; Application software; Capacitors; Circuits; Delay; Error correction; Power amplifiers; Sampling methods; Software radio; Voltage;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328133
