DocumentCode
3353509
Title
A low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range
Author
Movahedian, Hamid ; Azin, Meysam ; Bakhtiar, Mehrdad Sharif
Author_Institution
Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran
Volume
1
fYear
2004
fDate
23-26 May 2004
Abstract
An 8-bit 100MSample/s folding/interpolating ADC is presented. Using a new method incorporating both P and N folding blocks. The input voltage range of the ADC is increased to 1.1V, with a supply voltage of 1.5V. Implemented in a 0.15 μm digital CMOS process, simulation results show an INL below ±0.3 LSB, SNDR of 40.7dB at 100MHz sampling frequency and power dissipation of 35 mW.
Keywords
CMOS integrated circuits; analogue-digital conversion; interpolation; low-power electronics; 0.15 microns; 1.1 V; 1.5 V; 35 mW; 8 bit; digital CMOS; folding ADC; folding blocks; interpolating ADC; low power ADC; low voltage ADC; rail-to-rail input range; CMOS process; CMOS technology; Capacitance; Frequency; Impedance matching; Low voltage; Power dissipation; Rail to rail inputs; Sampling methods; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328135
Filename
1328135
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