DocumentCode
3353818
Title
A dynamic analysis of a latched CMOS comparator
Author
Samid, Lourans ; Volz, Patrick ; Manoli, Yiannos
Author_Institution
Microelectron., Freiburg Univ., Germany
Volume
1
fYear
2004
fDate
23-26 May 2004
Abstract
In the implementation of high-performance CMOS over-sampling A/D converters, high-speed comparators are indispensable. This paper discusses the design and analysis of a low-power regenerative latched CMOS comparator, based on an analytical approach which gives a deeper insight into the associated trade-offs. Calculation details and simulation results for a 20 MHz clocked comparator in a 0.5μm technology are presented.
Keywords
CMOS integrated circuits; analogue-digital conversion; circuit analysis computing; comparators (circuits); 0.5 microns; 20 MHz; clocked comparator; dynamic analysis; high-performance CMOS; high-speed comparators; latched CMOS comparator; low-power CMOS comparator; over-sampling ADC; regenerative CMOS comparator; Circuit simulation; Clocks; Costs; Energy consumption; Latches; Medical simulation; Microelectronics; Power dissipation; Switches; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN
0-7803-8251-X
Type
conf
DOI
10.1109/ISCAS.2004.1328161
Filename
1328161
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