A CMOS low-power ADC for DVB-T and DVB-H systems

Author

Adeniran, Olujide A. ; Demosthenous, Andreas ; Clifton, Chris ; Atungsiri, Sam ; Soin, Randeep

Author_Institution

Sony Semicond. & Electron. Solutions, Hampshire, UK

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

This paper describes the design of a 10-bit, 25MS/s analogue-to-digital converter (ADC) suitable for digital video broadcasting over terrestrial (DVB-T) and handheld (DVB-H) systems. The ADC is based on a 4-3-3-stage pipeline architecture and employs dynamic comparators and Miller-hold sample-and-hold amplifiers for high-speed operation and low-power consumption. Simulated results in a 0.35μm CMOS process show that the converter achieves 56dB signal-to-noise ratio(SNR) and 57dB spurious-free dynamic range (SFDR). The converter input range is 2V peak-to-peak differential and the total power consumption is 27mW from a 2.8V power supply.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); digital video broadcasting; high-speed integrated circuits; low-power electronics; pipeline processing; sample and hold circuits; 0.35 microns; 10 bit; 2 V; 2.8 V; 27 mW; 56 dB; CMOS; DVB-H systems; Miller-hold sample-and-hold amplifiers; digital video broadcasting over handheld; digital video broadcasting over terrestrial; dynamic comparators; high-speed operation; low-power ADC; low-power consumption; pipeline architecture; Analog-digital conversion; Bandwidth; Baseband; Demodulation; Digital video broadcasting; Energy consumption; Personal digital assistants; Pipelines; Power supplies; Tuners;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328168

Filename

1328168