Title :
Gate oxide scaling limits and projection
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
MOSFET gate oxide scaling limits are examined with respect to time-dependent breakdown, defects, plasma process damage, mobility degradation, poly-gate depletion, inversion layer thickness, tunneling leakage, charge trapping, and gate delay. It is projected that the operating field will stay around 5 MV/cm for reliability and optimum speed. Tunneling leakage prevents scaling below 2 nm, which is sufficient for MOSFET scaling to 0.05 /spl mu/m.
Keywords :
MOSFET; carrier mobility; electric breakdown; inversion layers; leakage currents; semiconductor device reliability; tunnelling; MOSFET; charge trapping; gate oxide scaling limits; inversion layer thickness; mobility degradation; operating field; plasma process damage; poly-gate depletion; reliability; time-dependent breakdown; tunneling leakage; Capacitance; Electric breakdown; MOSFET circuits; Physics; Plasma applications; Plasma sources; Predictive models; Special issues and sections; Tunneling; Voltage;
Conference_Titel :
Electron Devices Meeting, 1996. IEDM '96., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3393-4
DOI :
10.1109/IEDM.1996.553593
