Title :
High-throughput dual-mode single/double binary map processor design for wireless wan
Author :
Chen, Chun-Yu ; Lin, Cheng-Hung ; Wu, An-Yeu
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high throughput. A 1.28 mm2 dual-mode (SB/DB) 2PW-1HW MAP processor is also implemented in TSMC 0.13 mum CMOS process to verify the proposed approaches. The proposed MAP processor can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy.
Keywords :
VLSI; decoding; radio networks; turbo codes; wide area networks; VLSI implementation; double-binary convolutional turbo codes; high-throughput enhanced Max-log-MAP processor; hybrid-window MAP decoding; parallel-window MAP decoding; single-binary convolutional turbo codes; wireless WAN; CMOS process; Convolutional codes; Costs; Decoding; Hardware; Process design; Throughput; Turbo codes; Very large scale integration; Wide area networks; hardware accelerators; maximum a-posteriori probability; turbo codes;
Conference_Titel :
Signal Processing Systems, 2008. SiPS 2008. IEEE Workshop on
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4244-2923-3
Electronic_ISBN :
1520-6130
DOI :
10.1109/SIPS.2008.4671742
