High-throughput dual-mode single/double binary map processor design for wireless wan

Author

Chen, Chun-Yu ; Lin, Cheng-Hung ; Wu, An-Yeu

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei

fYear

2008

fDate

8-10 Oct. 2008

Firstpage

83

Lastpage

87

Abstract

In this paper we present the VLSI implementation of a high-throughput enhanced Max-log-MAP processor that supports both single-binary (SB) and double-binary (DB) convolutional turbo codes. The combined hybrid-window (HW) and parallel-window (PW) MAP decoding is introduced to support arbitrary frame sizes with high throughput. A 1.28 mm² dual-mode (SB/DB) 2PW-1HW MAP processor is also implemented in TSMC 0.13 mum CMOS process to verify the proposed approaches. The proposed MAP processor can be used as hardware accelerators in multistandard platform for wireless WAN with low cost and low energy.

Keywords

VLSI; decoding; radio networks; turbo codes; wide area networks; VLSI implementation; double-binary convolutional turbo codes; high-throughput enhanced Max-log-MAP processor; hybrid-window MAP decoding; parallel-window MAP decoding; single-binary convolutional turbo codes; wireless WAN; CMOS process; Convolutional codes; Costs; Decoding; Hardware; Process design; Throughput; Turbo codes; Very large scale integration; Wide area networks; hardware accelerators; maximum a-posteriori probability; turbo codes;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2008. SiPS 2008. IEEE Workshop on

Conference_Location

Washington, DC

ISSN

1520-6130

Print_ISBN

978-1-4244-2923-3

Electronic_ISBN

1520-6130

Type

conf

DOI

10.1109/SIPS.2008.4671742

Filename

4671742