A process, voltage, and temperature compensated CMOS constant current reference

Author

Sengupta, S. ; Saurabh, K. ; Allen, P.E.

Author_Institution

Dept. of Electr. & Comput. Eng.,, Georgia Inst. of Technol., Atlanta, GA, USA

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

In this paper, a CMOS constant current reference over PVT (process, voltage and temperature) variations is presented. The drain current of a MOS device gives the reference current, which is compensated for process variations by exploiting the physical relationship between K´(μC_ox) and V_T across various process corners. It is also compensated for power supply and temperature variations by a PTAT voltage reference, which aids in the generation of the reference current. In order to prove the proposed concept, simulation results from 0.25 μm, 0.18 μm, 0.13 μm, and 90 nm CMOS processes are presented.

Keywords

CMOS integrated circuits; compensation; reference circuits; 0.13 micron; 0.18 micron; 0.25 micron; 90 nm; CMOS processes; MOS device; PTAT; PVT variations; constant current reference; drain current; power supply compensation; process variations; temperature variations; voltage reference; CMOS process; Circuit optimization; Doping; Equations; MOS devices; Power generation; Power supplies; TV; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328197

Filename

1328197