DocumentCode
3354401
Title
Design of a hot wall-based low temperature annealing system and its process applications
Author
Yoo, Woo Sik ; Fukada, Takashi ; Murakami, Tomomi ; Kang, Kitaek ; Foggiato, John
Author_Institution
WaferMasters Inc., San Jose, CA
fYear
2004
fDate
2004
Firstpage
89
Lastpage
93
Abstract
A hot wall-based low temperature annealing system using resistively heated, stacked hot plates was designed and tested for low temperature (100~500degC) annealing applications for 200 mm and 300 mm wafers. The system is designed to process five wafers simultaneously for productivity enhancement purposes. Thermal properties of the system and wafer temperature profiles during low temperature annealing in stacked hot plates were characterized as a function of hot plate temperature. The stacked hot plate configuration with proper gap between wafer and surrounding hot plates makes convection heat transfer predominant and provides uniform and repeatable process results in the low temperature region. Process uniformity and repeatability of NiSi formation, Cu annealing, Al sintering, spin-on-dielectrics (SOD) anneal were confirmed in the temperature range of 100~500degC
Keywords
aluminium; annealing; convection; copper; dielectric materials; elemental semiconductors; nickel alloys; semiconductor process modelling; silicon; silicon alloys; sintering; 100 to 500 degC; 200 mm; 300 mm; Al; Cu; NiSi; convection heat transfer; hot wall-based low temperature annealing system; resistively heated plates; sintering; spin-on-dielectrics anneal; stacked hot plates; thermal properties; Annealing; Control systems; Copper; Heat transfer; Process control; Process design; Productivity; Temperature control; Temperature distribution; Thermal conductivity;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Thermal Processing of Semiconductors, 2004. RTP 2004. 12th IEEE International Conference on
Conference_Location
Portland, OR
Print_ISBN
0-7803-8477-6
Type
conf
DOI
10.1109/RTP.2004.1441941
Filename
1441941
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