DocumentCode :
3354430
Title :
Wafer testing with pairwise comparisons
Author :
Huang, K. ; Agarwal, V.K. ; LaForge, L. ; Thulasiraman, H.
Author_Institution :
McGill Univ., Montreal, Que., Canada
fYear :
1992
fDate :
8-10 July 1992
Firstpage :
374
Lastpage :
383
Abstract :
A novel diagnosis scheme is proposed for wafer testing, in which the test access port of each die is utilized to perform comparison tests on its neighbors. A probabilistic diagnosis algorithm is presented, which correctly identifies almost all dies, even when the probability of failure of a die is larger than 0.5. The algorithm is shown to be particularly suitable for constant degree structures, such as rectangular and octagonal grids. The algorithm is designed for wafer scale structures, where the boundary dies do not have a complete regular structure. The algorithm also allows for the fault coverage of the tests to be imperfect. In addition, diagnosis is done locally. Both the test time and the diagnosis time are invariant with respect to the number of dies on the wafer. The algorithm can also tolerate some systematic errors. The dies are tested in parallel with this approach.<>
Keywords :
fault location; integrated circuit testing; comparison tests; constant degree structures; diagnosis scheme; die; fault coverage; octagonal grids; pairwise comparisons; probabilistic diagnosis algorithm; probability of failure; rectangular grids; systematic errors; test access port; wafer scale structures; wafer testing; Algorithm design and analysis; Automatic testing; Built-in self-test; Costs; Digital systems; Electronics industry; Hypercubes; Performance evaluation; Semiconductor device testing; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on
Conference_Location :
Boston, MA, USA
Print_ISBN :
0-8186-2875-8
Type :
conf
DOI :
10.1109/FTCS.1992.243563
Filename :
243563
Link To Document :
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