A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems

Author

Sin, Sai-Weng ; Seng-Pan, U. ; Martins, R.P.

Author_Institution

Fac. of Sci. & Technol., Macau Univ., China

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

This paper presents a comprehensive analysis of mismatch-insensitive clock generation techniques for general parallel sampled-data systems. Two jitter-insensitive clock generation schemes are described, a class of multi-purpose, low-jitter, multi-phase clock generator platform is proposed. The platform can provide clock phases for the two pre-described clock generation schemes and has the advantages of being insensitive to timing mismatches, having a simple and highly robust architecture such that the clock generator can be generalized not only for an arbitrary number N of time-interleaved (TI) paths, but also can be applied to general TI sampled data systems including ADCs, DACs and N-path filters.

Keywords

analogue-digital conversion; circuit analysis computing; clocks; digital-analogue conversion; filters; sampled data circuits; signal sampling; timing jitter; ADC; DAC; N-path filters; arbitrary number; clock phases; comprehensive analysis; generalized clock generation; jitter-insensitive clock generation; low-jitter clock generation; mismatch-insensitive clock generation; multiphase clock generation; multiphase clock generator platform; multipurpose clock generation; parallel sampled-data systems; robust architecture; time-interleaved paths; timing mismatches; timing-skew-free clock generation; Circuits; Clocks; Electronic mail; Frequency; Image sampling; Robustness; Sampled data systems; Sampling methods; Signal generators; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328208

Filename

1328208