Hardware/Software Partitioning of a Bayesian Spam Filter via Hardware Profiling

This paper explores the possibility of accelerating the operation of a Bayesian spam filter by moving parts of its functionality to hardware. Effort is done to produce a software C library that can support building a Bayesian spam filter. Then, a software Bayesian spam filter was implemented and run on the Microblaze processor soft-core on a Xilinx FPGA. This constitutes a first step towards designing an efficient spam filtering platform based on the Microblaze processor. Profiling the Bayesian spam filter on hardware gives insights on possibilities for accelerating it. Some functions are recommended to be moved to hardware, reconfigurable hardware, or parallel hardware solutions. We found that implementing a hardware hash table or parallel reconfigurable hardware tokenization function can improve the performance of a Bayesian spam filter. When the hash table was replaced by a content addressable memory, the overall performance achieved an average improvement of 10%