• DocumentCode
    3354526
  • Title

    A study of the effects of transient fault injection into a 32-bit RISC with built-in watchdog

  • Author

    Ohlsson, J. ; Rimen, M. ; Gunneflo, U.

  • Author_Institution
    Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
  • fYear
    1992
  • fDate
    8-10 July 1992
  • Firstpage
    316
  • Lastpage
    325
  • Abstract
    An error-detecting 32-b reduced instruction set computer (RISC) designed in a 1.2- mu m CMOS technology with an on-chip watchdog using embedded signature monitoring is presented. It was evaluated through simulation-based fault injection, using a register level model written in VHDL (very high-speed IC (VHSIC) description language). A chip area increase of 4.7% was caused by the watchdog. Two application programs were executed to study workload dependencies. The insertion of watchdog instructions resulted in a memory overhead of between 13% and 25% as well as a performance overhead of between 9% and 19%. A total of 2779 faults were injected into the processor during execution of the application programs. Only 23% of these resulted in effective errors. A minimum detection coverage of 95% was reached for effective errors classified as control flow errors with a median latency of one clock cycle. Few effective data errors, between 22% and 50%, were detected.<>
  • Keywords
    CMOS integrated circuits; fault location; fault tolerant computing; reduced instruction set computing; specification languages; 1.2 micron; 32 bit; 32-bit RISC; CMOS technology; VHDL; application programs; built-in watchdog; embedded signature monitoring; median latency; memory overhead; minimum detection coverage; performance overhead; register level model; transient fault injection; very high-speed IC; CMOS technology; Computational modeling; Computer aided instruction; Computer errors; Computerized monitoring; Embedded computing; Error correction; Integrated circuit modeling; Reduced instruction set computing; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on
  • Conference_Location
    Boston, MA, USA
  • Print_ISBN
    0-8186-2875-8
  • Type

    conf

  • DOI
    10.1109/FTCS.1992.243569
  • Filename
    243569