Title :
Low-voltage linear voltage regulator suitable for memories
Author :
Aloisi, W. ; Billé, S.M. ; Palumbo, G.
Author_Institution :
DIEES, Universita di Catania, Italy
Abstract :
In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffer from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 μm standard CMOS technology. The regulator can work with a no-regulated input voltage in the range from 1.3 V to 3 V providing a regulated voltage of 1 V with a load capacitance of 2.2 nF.
Keywords :
CMOS analogue integrated circuits; analogue integrated circuits; capacitance; integrated circuit design; low-power electronics; voltage regulators; 0.35 micron; 1 V; 1.3 to 3 V; 2.2 nF; CMOS technology; class-AB gain stage; internal slew-rate limitation; linear voltage regulator; load capacitance; low-voltage regulator; memory application; Analog circuits; CMOS technology; Capacitance; Mirrors; Operational amplifiers; Power supplies; Regulators; Signal analysis; Transconductors; Voltage;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328213
