Error-resilient low-power Viterbi decoders via state clustering

Low-power Viterbi decoder (VD) architectures based on the principle of error-resiliency are presented in this paper. Power reduction in the add-compare-select units (ACSUs) of a VD is achieved by either overscaling the supply voltage (voltage overscaling (VOS)) or designing at the nominal process corner and supply voltage (average-case design). In either case, the data-dependent timing errors which occur whenever a critical path is excited, are corrected via the application of algorithmic noise-tolerance (ANT). The concept of state clustering is employed to develop efficient estimators for error-correction. Power savings achieved in the presence of VOS and process variations are 71% and 62%, respectively, at a loss of 0.8 dB and 0.6 dB in coding gain in a IBM 130 nm CMOS process.