Title :
Testing with correlated test vectors
Author :
Bou-Ghazale, S. ; Marinos, P.N.
Author_Institution :
IBM Corp., Boca Raton, FL, USA
Abstract :
The authors present a new built-in self-test (BIST) strategy based on correlated test vectors produced by a weighted random test-pattern generator. It is demonstrated that use of correlated test vectors reduces greatly the hardware complexity of the generator without causing significant degradation in the test outcome. Performance evaluation of this BIST technique is carried out quantitatively via probabilistic methods, and experimentally through deterministic fault simulation. Correlated weighted test patterns using the proposed scheme were applied to the ISCAS 1985 benchmark circuits, and comparisons are made to test results obtained using such techniques as WARP and GSCAN.<>
Keywords :
built-in self test; logic testing; GSCAN; ISCAS 1985 benchmark circuits; WARP; built-in self-test; correlated test vectors; deterministic fault simulation; hardware complexity; performance evaluation; probabilistic methods; weighted random test-pattern generator; Automatic testing; Benchmark testing; Built-in self-test; Circuit faults; Circuit simulation; Circuit testing; Degradation; Hardware; Test pattern generators; Upper bound;
Conference_Titel :
Fault-Tolerant Computing, 1992. FTCS-22. Digest of Papers., Twenty-Second International Symposium on
Conference_Location :
Boston, MA, USA
Print_ISBN :
0-8186-2875-8
DOI :
10.1109/FTCS.1992.243576
