A FPGA-based emulation of the Timing Trigger and control receiver for the LHC experiments

The Timing Trigger and Control (TTC) system is a crucial part of all the experiments at the Large Hadron Collider (LHC). It is an optical distribution network which delivers to the detectors´ electronics, with low jitter and skew, the timing and synchronization signals of the LHC machine and the trigger information of the experiments. Unfortunately, some elements of the system have now become obsolete, as they were designed in the 90´s with old technologies and components. Specifically only a small amount of the network receivers (TTCrx) is still available for the experiments. In this paper we present a possible solution to replace the TTCrx features, to be used on the off-detector electronics, where radiation is not a concern. We show an implementation based on the last generation FPGAs, using FPGA fabric and embedded high speed serial link transceivers, in order to emulate the architecture and the features of the TTCrx. With this approach, the receiver part of the TTC can be emulated and embedded in commercially available FPGAs, thus reducing the complexity of the electronics boards and allowing the user to easily replicate the TTCrx features with commercial devices. We discuss the details of the implementation and show preliminary test results.