Title :
Low kickback noise techniques for CMOS latched comparators
Author :
Figueiredo, Pedro M. ; Vital, João C.
Author_Institution :
Chipidea Microelectron.,, Porto Salvo, Portugal
Abstract :
The latched comparator is utilized in virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. Such high voltage variations in the regeneration nodes are coupled to the input voltage - kickback noise. This paper reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations verify the effectiveness of our techniques.
Keywords :
CMOS integrated circuits; SPICE; comparators (circuits); integrated circuit noise; CMOS latched comparators; HSPICE simulation; analog input signal regeneration; analog-to-digital converter; full-scale digital level; high voltage variation; input voltage; kickback noise minimization; positive feedback mechanism; regeneration nodes; Analog-digital conversion; CMOS technology; Clocks; Coupling circuits; Degradation; Feedback; Impedance; Inverters; Parasitic capacitance; Voltage;
Conference_Titel :
Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on
Print_ISBN :
0-7803-8251-X
DOI :
10.1109/ISCAS.2004.1328250
