A low-power DC-7-GHz SOI CMOS distributed amplifier

Author

Zencir, Ertan ; Tekin, Ahmet ; Dogan, Numan S. ; Arvas, Ercument

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina A&T State Univ., Greensboro, NC, USA

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

A low-power DC-7-GHz distributed amplifier design with on-chip inductor models was realized in a 0.35-μm silicon on insulator (SOI) CMOS process. The amplifier has simulated unity-gain cutoff frequency of 7 GHz. The gain is 5.8 dB, with a gain flatness of ±0.7 dB over the DC-6.3-GHz range. The noise figure minimum value is 3.4 dB occurring at 2.8 GHz. At 6.3 GHz, the noise figure is 6 dB. The input-referred 1-dB compression point varies in the range of 10-3 dBm from DC to 7 GHz. Total power dissipation is 50 mW from a 3-V drain supply voltage. This distributed amplifier features as the first design realized in SOI CMOS and with the lowest power dissipation claimed so far.

Keywords

CMOS integrated circuits; circuit simulation; distributed amplifiers; elemental semiconductors; inductors; integrated circuit design; low-power electronics; silicon-on-insulator; system-on-chip; 0.35 micron; 2.8 GHz; 3 V; 3.4 dB; 5.8 dB; 50 mW; 6 dB; 6.3 GHz; 7 GHz; SOI CMOS; amplifier simulation; gain flatness; low-power DC distributed amplifier; on-chip inductor model; power dissipation; silicon on insulator CMOS process; unity-gain cutoff; CMOS process; Cutoff frequency; Distributed amplifiers; Gain; Inductors; Noise figure; Power dissipation; Semiconductor device modeling; Silicon on insulator technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328267

Filename

1328267