DocumentCode
3356913
Title
Packaging of multi-core microprocessors: tradeoffs and potential solutions
Author
Muthana, Prathap ; Swaminathan, Madhavan ; Tummala, Rao ; Sundaram, Venkatesh ; Wan, Lixi ; Bhattacharya, S.K. ; Raj, P.M.
Author_Institution
Sch. of Electr. & Comput. Eng. Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2005
fDate
31 May-3 June 2005
Firstpage
1895
Abstract
Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multicore processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade offs between single and multicore processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.
Keywords
integrated circuit packaging; microprocessor chips; interconnect latency; multicore microprocessor packaging; power consumption; Bandwidth; Delay; Energy consumption; Frequency; High performance computing; Microprocessors; Multicore processing; Packaging; Performance analysis; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2005. Proceedings. 55th
ISSN
0569-5503
Print_ISBN
0-7803-8907-7
Type
conf
DOI
10.1109/ECTC.2005.1442057
Filename
1442057
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