1.2V low-power four-quadrant CMOS transconductance multiplier operating in saturation region

Author

Szczepanski, S. ; Koziel, S.

Author_Institution

Fac. of Electron., Telecommun. & Inf., Gdansk Univ. of Technol., Poland

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

The paper describes a simple CMOS technique for realizing a linear, low-voltage, low-power, four-quadrant transconductance multiplier based on MOS transistors working in saturation region. The proposed circuit has been developed and simulated using standard 0.35μm AMS process. SPICE simulations show that the total harmonic distortion (THD) at 0.3V_pp@1MHz applied to Y input is -70.5dB with 0.1V DC voltage applied to X input. Input referred noise equals 0.6μV/Hz¹2/ which results in the dynamic range of the circuit equal to 52dB. Power consumption is 0.05mW from a single 1.2V supply. An example of application the CMOS multiplier as a modulator is presented.

Keywords

CMOS analogue integrated circuits; MOSFET; analogue multipliers; low-power electronics; 0.05 mW; 0.1 V; 0.35 micron; 1 MHz; 1.2 V; AMS process; CMOS technique; MOS transistors; SPICE simulations; four-quadrant CMOS transconductance multiplier; input referred noise; saturation region; total harmonic distortion; CMOS technology; Circuit noise; Circuit simulation; Dynamic range; MOSFETs; SPICE; Standards development; Total harmonic distortion; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328370

Filename

1328370