A 0.8V CMOS analog decoder for an (8,4,4) extended Hamming code

Author

Nguyen, Nhan ; Winstead, Chris ; Gaudet, Vincent C. ; Schlegel, Christian

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

Volume

1

fYear

2004

fDate

23-26 May 2004

Abstract

A soft decoding method for iterative error control codes is through the use of analog circuits. Analog decoders exploit the nonlinear behaviour of transistors operating in subthreshold to process probability information. This paper describes the design of an (8,4,4) extended Hamming decoder operating at supply voltage 0.8V using 0.18μm CMOS technology. When normalizers are biased at 1μA, a decoding rate of 444 kbps and energy per decoded bit of 0.64nJ/b is achieved.

Keywords

CMOS analogue integrated circuits; Hamming codes; analogue processing circuits; graphs; iterative decoding; transistors; 0.18 micron; 0.8 V; 1 muA; CMOS technology; Hamming code; Hamming decoder; analog circuits; analog decoder; iterative error control codes; nonlinear behaviour; probability information processing; soft decoding method; transistors; Analog circuits; CMOS technology; Error correction; Floors; Iterative decoding; Iterative methods; Maximum likelihood decoding; Parity check codes; Probability distribution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1328395

Filename

1328395