ASIC design of a progressive vector quantizer

The authors describe the architecture of a real-time progressive full-search vector quantizer (VQ) suitable for VLSI implementation. Because of the large memory and ALU requirements of a single VQ, the compression is performed in stages. Each stage generates a codebook index, a difference vector, and total pixel error squared. The encoder chip is partitioned into master/slave portions dividing the codebooks and computational requirements between the two ASICs (application-specific integrated circuits). Because the system is modular, several encoder stages can be cascaded to achieve a higher-quality reconstruction. The VQ is progressive in the sense that each additional stage of encoding produces better visual quality. The authors also describe the architecture of a completion chip which can be used in conjunction with several encoders to realize a single VQ