Synthesis of pipelined SRSL circuits

In this paper, we propose a new design methodology for clockless circuits based on the present methodology of clocked circuits. This methodology takes advantage of the maturity of current CAD tools to synthesize new clockless pipelines without disrupting their design flow. Currently, there is no established design methodology to support the design and verification of clockless circuits. As a case in study, the proposed design methodology targets the synthesis of new pipelines based on a recently introduced clockless design technique called self-resetting stage logic (SRSL). The synthesis of SRSL pipelines starts from a synthesized gate netlist to satisfy a specified data rate by minimizing overall pipeline area. Since this synthesis problem is formulated as a large integer programming problem, an efficient two-phase heuristic algorithm is proposed to solve this problem. Experimental results show that SRSL pipelines can reach throughputs in the GHz range and are highly suitable for coarse-grain datapaths