Title :
A "soft++" eFPGA physical design approach with case studies in 180nm and 90nm
Author :
Aken´Ova, V. ; Saleh, R.
Author_Institution :
Dept. of Electr. & Comput. Eng., British Columbia Univ.
Abstract :
Our recent work in embedded FPGAs has been focused on a soft IP approach where programmable fabrics are described at the RTL level and implemented using the ASIC digital flow and generic standard cells. Early results showed significant penalties in area, delay, and power overhead. However, using tactical standard cells and a structured physical design approach within such a flow, we were able to obtain large savings in area and delay. We defined this new approach as soft++ eFPGA. This paper provides details of the physical design flow, with particular emphasis on floor-planning, interconnect-planning, and clock tree synthesis. The advantages of our approach in handling larger circuits are demonstrated on a set of realistic benchmark circuits implemented in 180nm and 90nm CMOS process technology
Keywords :
CMOS logic circuits; embedded systems; field programmable gate arrays; integrated circuit layout; logic design; 180 nm; 90 nm; ASIC digital flow; CMOS technology; RTL level; clock tree synthesis; embedded FPGA; floorplanning; generic standard cells; interconnect-planning; programmable fabrics; soft++ eFPGA; Application specific integrated circuits; Computer aided software engineering; Costs; Delay; Fabrics; Field programmable gate arrays; Integrated circuit interconnections; Logic design; Programmable logic arrays; Programmable logic devices;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.1
