Design and analysis of a low power VLIW DSP core

Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuit-level. In order to develop a power efficient system, architecture design, compiler optimization, as well as user evaluation must be employed in a unified framework. This paper presents an architecture-level power/performance simulator for a VLIW DSP processor core. Relying on parameterized power models and cycle accurate simulation, it provides fast and accurate power estimation for architecture exploration. Furthermore, the proposed modeling methodology can be used with minimal changes in the evaluation of other VLIW processor cores or for characterizing the efficiency of compiler-driven power efficient transformations.