DocumentCode :
3358665
Title :
A low power pipelined maximum likelihood detector for 4/spl times/4 QPSK MIMO wireless communication systems
Author :
Han, J.H. ; Erdogan, A.T. ; Arslan, T.
Author_Institution :
Sch. of Eng. & Electron., Edinburgh Univ.
fYear :
2006
fDate :
2-3 March 2006
Abstract :
The authors present a maximum likelihood (ML) detector for multiple-input multiple-output (MIMO) wireless communication systems. The ML detector has been specifically designed to reduce the implementation complexity without significant degradation in bit error rate (BER) performance. In order to identify the optimized fixed-point representation, the ML detector has been simulated with various representations for the received data. The computation process of the channel matrix and constellation symbols in ML detector is simplified by using normalized symbols. Simulation results are provided showing 42% saving in area usage and 68% saving in power consumption compared to a conventional architecture
Keywords :
MIMO systems; channel estimation; fixed point arithmetic; low-power electronics; maximum likelihood detection; quadrature phase shift keying; wireless channels; QPSK MIMO systems; bit error rate; channel matrix; constellation symbols; fixed-point representation; maximum likelihood detector; multiple-input multiple-output systems; wireless communication systems; Bit error rate; Computational modeling; Computer architecture; Degradation; Detectors; Energy consumption; MIMO; Maximum likelihood detection; Quadrature phase shift keying; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
Type :
conf
DOI :
10.1109/ISVLSI.2006.4
Filename :
1602438
Link To Document :
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