Title :
Optimal periodical memory allocation for logic-in-memory image processors
Author :
Hariyama, M. ; Kameyama, M. ; Kobayashi, Y.
Author_Institution :
Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai
Abstract :
One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design methodology for a logic-in-memory architecture where each of memory modules is connected to its dedicated processing element (PE). An efficient memory allocation to minimize the number of memory modules and PEs under a time constraint is proposed based on regularity
Keywords :
digital storage; image processing equipment; logic design; memory architecture; microprocessor chips; storage management; logic-in-memory architecture; logic-in-memory image processors; memory modules; periodical memory allocation; processing element; Design methodology; Educational institutions; Logic; Multiprocessor interconnection networks; Process design; Road vehicles; Search methods; Spatial filters; Time factors; Very large scale integration;
Conference_Titel :
Emerging VLSI Technologies and Architectures, 2006. IEEE Computer Society Annual Symposium on
Conference_Location :
Karlsruhe
Print_ISBN :
0-7695-2533-4
DOI :
10.1109/ISVLSI.2006.69
