Title :
Process variability at the 65nm node and beyond
Author_Institution :
IBM Austin Res. Lab., Austin, TX
Abstract :
The impact of manufacturing-induced variations has been well established as a first order impediment to modern integrated circuit design [1]. Numerous research efforts are currently underway to (a) understand and characterize variability[2], to (b) predict its impact on circuit behavior[3], and (c) to develop layout and circuit design techniques to reduce the impact of variability[4]. Simultaneously, except for the most advanced high performance designs, the increasing cost of migrating to sub-65 nm technology nodes is slowing down adoption of advanced technologies. This slow down is allowing current efforts to catch up and help mitigate variability as an impediment.
Keywords :
integrated circuit design; integrated circuit layout; catastrophic faults; integrated circuit design; manufacturing-induced variability; process variability; size 65 nm; variability impact; CMOS technology; Costs; Impedance; Integrated circuit interconnections; Investments; Laboratories; MOSFET circuits; Manufacturing processes; Switches; USA Councils;
Conference_Titel :
Custom Integrated Circuits Conference, 2008. CICC 2008. IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-2018-6
Electronic_ISBN :
978-1-4244-2019-3
DOI :
10.1109/CICC.2008.4672005
